CMOS diodes are important passive components in modern integrated circuit (IC) devices. The diode is also used in bandgap reference circuits, requiring a tight range of specification of the device parameters.
In FIG. 1, a prior art CMOS diode 100 is shown. CMOS diode 100 is comprised of a silicon substrate 102. Region 104 of the substrate is doped with an N+ species to form an N doped region (also referred to as an N+ region), and region 107 is doped with a P+ species to form a P doped region (also referred to as a P+ region). Region 106 remains as the original N type silicon substrate. A polysilicon gate structure 108 is disposed above region 106, and in between regions 104 and 106. The polysilicon gate structure 108 is comprised of a N+ region 110, and a P+ region 112. Spacer structures 114 and 116 are adjacent to the respective doped regions. As is known in the art, spacer 116, which is adjacent to P+ region 112 may be of a different shape than spacer 114, which is adjacent to N+ region 110. Silicide regions 118, 120, and 122 are all comprised of a similar material, and disposed on the silicon substrate to form contacts. Silicide region 118 forms the anode contact of diode 100, and silicide region 122 forms the cathode contact of the diode 100. Silicide region 120 is formed over the gate structure 118. Electrical connections 126A and 126B connect the gate contact 120 to the anode contact 118 to ground point 126C, thereby rendering the gate contact 120 as “unused.” Note that references 126A, 126B, and 126C are schematically indicated, and are not representative of a physical structure in the device. Nitride layer 124 is deposited on the silicon substrate 102, silicide regions 118, 120, and 122, and gate structure 108.
It should clearly be understood that FIG. 1 illustrates but an extremely small (microscopic) portion of an integrated circuit (IC) device, let alone a semiconductor wafer comprising a large plurality of such devices. For example, what is shown may have a width of only a few microns of a semiconductor wafer having a diameter of several inches. Also, in “real life” things are not so neat and clean, rectilinear and uniform as shown. However, for one of ordinary skill in the art to which the invention most nearly pertains, this and other figures presented in this patent application will be very useful, when taken in context of the associated descriptive text, for understanding the invention.
As device dimensions continue to shrink, contact resistance between region 118 and 104, and between region 122 and 108 increases to the point where it starts to dominate the total resistance of the device, resulting in reduced device current. It also adversely impacts device variations that result from the increase resistance variation. Therefore, what is needed is a new diode structure providing reduced contact resistance while also providing the capability for reduced device size.